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ics9250-19 third party brands and names are the property of their respective owners. integrated circuit systems, inc. block diagram frequency generator & integrated buffers for celeron & p ii / iii ? 9250-19 rev c 4/12/01 functionality pin configuration recommended application: bx, appollo pro 133 type of chip set. output features: ? 3 - cpus @2.5v, up to 150mhz. 17 - sdram @ 3.3v, up to 150mhz. 7 - pci @3.3v 2 - ioapic @ 2.5v 1 - 48mhz, @3.3v fixed. 1 - 24mhz @ 3.3v 2 - ref @3.3v, 14.318mhz. features: up to 150mhz frequency support support power management: cpu, pci, stop and power down mode form i 2 c programming. spread spectrum for emi control (0 to -0.5%, 0.25%). uses external 14.318mhz crystal key specifications: cpu ? cpu: <175ps cpu ? pci: 1 - 4ns pci ? pci: <500ps sdram - sdram: <250ps 56-pin ssop * internal pull-up resistor of 240k to 3.3v on indicated inputs ** internal pull-down resistor of 240k to gnd on indicated inputs. 3 s f2 s f1 s f0 s f u p c ) z h m ( ) z h m ( k l c i c p 1111 3 3 1) 4 / u p c ( 3 . 3 3 1110 4 2 1) 4 / u p c ( 1 3 1101 0 5 1) 4 / u p c ( 5 . 7 3 1100 0 4 1) 4 / u p c ( 5 3 10 11 5 0 1) 3 / u p c ( 5 3 10 10 0 1 1) 3 / u p c ( 7 6 . 6 3 100 1 5 1 1) 3 / u p c ( 3 3 . 8 3 1000 0 2 1) 3 / u p c ( 0 0 . 0 4 0111 0 . 0 0 1) 3 / u p c ( 3 4 . 3 3 0110 3 3 1) 3 / u p c ( 3 3 . 4 4 0101 2 1 1) 3 / u p c ( 3 3 . 7 3 0100 3 0 1) 2 / u p c ( 3 3 . 4 3 0011 6 . 6 6) 2 / u p c ( 0 4 . 3 3 0010 3 . 3 8) 2 / u p c ( 5 6 . 1 4 0001 5 7) 2 / u p c ( 5 . 7 3 0000 4 2 1) 2 / u p c ( 3 3 . 1 4 ics reserves the right to make changes in the device data identified in this publication without further notice. ics advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.
2 ics9250-19 third party brands and names are the property of their respective owners. pin configuration notes: 1: bidirectional input/output pins, input logic levels are latched at internal power-on-reset. use 10kohm resistor to program logic hi to vdd or gnd for logic low. r e b m u n n i pe m a n n i pe p y tn o i t p i r c s e d 2 1 f e rt u ot u p t u o k c o l c e c n e r e f e r z h m 8 1 3 . 4 1 2 s f 1 n ii c p d d v o t p u - l l u p s a h . t u p n i t c e l e s y c n e u q e r f d e h c t a l 3 0 f e rt u ot u p t u o k c o l c e c n e r e f e r z h m 8 1 3 . 4 1 # p o t s _ i c pn i . w o l n e h w l e v e l " 0 " c i g o l t a ] 1 : 5 [ k l c i c p s t l a h ) 0 = e d o m , e l i b o m n i ( , 2 4 , 4 3 , 6 2 , 3 2 , 0 1 , 4 3 5 , 8 4 d n gr w p. d n u o r g 51 xn i. ) f p 3 3 l a n i m o n ( , p a c d a o l l a n r e t n i s a h . t u p n i z h m 8 1 3 . 4 1 62 xt u o k c a b d e e f d n a ) f p 3 3 ( p a c d a o l l a n r e t n i s a h . t u p t u o l a t s y r c 1 x o t r o t s i s e r 8 f _ k l c i c pt u o# p o t s _ i c p y b d e t c e f a t o n k c o l c s u b g n i n n u r e e r f e d o m 1 n i n e h w # p o t s _ i c p o t 3 n i p s t r e v n o c . t c e l e s e d o m r o f t u p n i d e h c t a l . t n e m e g a n a m r e w o p r o f w o l 9 3 s fn in w o d - l l u p , t u p n i t c e l e s y c n e u q e r f d e h c t a l 0 k l c i c pt u o# p o t s _ i c p y b d e t c e f a t o n k c o l c s u b g n i n n u r e e r f 1 1 , 2 1 , 3 1 , 4 1 , 6 1] 1 : 5 [ k l c i c pt u o. s t u p t u o k c o l c i c p 7 1n i r e f f u bn is r e f f u b r o f t u p n i 7 2a t a d sn ii ( . t r o p g i f n o c l a i r e s r o f n i a t a d l a i r e s 2 ) c 8 2k l c sn ii ( . t r o p g i f n o c l a i r e s r o f t u p n i k c o l c 2 ) c 0 3 z h m 4 2t u o. d f r o o / i r e p u s r o f t u p t u o k c o l c z h m 4 2 0 s f 1 n i. 4 d d v o t p u - l l u p s a h . t u p n i t c e l e s y c n e u q e r f d e h c t a l 9 2 z h m 8 4t u o. b s u r o f t u p t u o k c o l c z h m 8 4 1 s f 1 n i. 2 d d v o t p u - l l u p s a h . t u p n i t c e l e s y c n e u q e r f d e h c t a l , 0 2 , 5 1 , 7 , 1 , 1 35 4 , 7 3 , f e r d d v , i c p d d v 8 4 d d v , r d s d d v r w p. n o i t c n u f r o f s p u o r g r e w o p e e s , y l p p u s r e w o p v 3 . 3 l a n i m o n , 8 1 , 3 3 , 2 3 , 5 2 , 4 2 , 6 3 , 5 3 , 2 2 , 1 2 , 9 1 , 3 4 , 1 4 , 0 4 , 9 3 , 8 3 4 4 ] 0 : 5 1 [ m a r d st u os k c o l c m a r d s 6 4f _ m a r d st u o# p o t s _ u p c y b d e t c e f f a t o n k c o l c m a r d s g n i n n u r e e r f 7 4# p o t s _ u p cn i k l c u p c s t l a h] 0 : 5 1 [ m a r d s , 0 c i p a o i , ] 1 : 2 [ . w o l n e h w l e v e l " 0 " c i g o l t a s k c o l c 6 5 , 0 5 , u p c l d d v c i p a o i l d d v r w p. l a n i m o n v 5 . 2 , y l p p u s r e w o p r e f f u b k c o l c c i p a o i d n a u p c 5 50 c i p a o it u o1 l d d v y b d e r e w o p ) z h m 8 1 3 . 4 1 ( . t u p t u o k c o l c c i p a o i 9 4 , 1 5] 1 : 2 [ k l c u p ct u o) z h m 6 . 6 6 r o 0 6 ( 2 l d d v y b d e r e w o p . s k c o l c t u p t u o u p c 2 5f _ k l c u p ct u o. # p o t s _ u p c e h t y t d e t c e f f a t o n . k c o l c t u p t u o u p c g n i n n u r e e r f 4 5f _ c i p a o it u o g n i n n u r e e r f. t u p t u o k c o l c c i p a o i# p o t s _ u p c e h t y b d e t c e f f a t o n 1 l d d v y b d e r e w o p ) z h m 8 1 8 1 3 . 4 1 (
3 ics9250-19 third party brands and names are the property of their respective owners. general description the ics9250-19 is the single chip clock solution for desktop/designs using bx, appollo pro 133 type of chip sets. it provides all necessary clock signals for such a system. spread spectrum may be enabled through i 2 c programming. spread spectrum typically reduces system emi by 8db to 10db. this simplifies emi qualification without resorting to board design iterations or costly shielding. the ics9250-19 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations. serial programming i 2 c interface allows changing functions, stop clock programming and frequency selection. mode pin - power management input control e d o m ) t u p n i d e h c t a l ( 0 # p o t s _ i c p ) t u p n i ( 1 0 f e r ) t u p t u o (
4 ics9250-19 third party brands and names are the property of their respective owners. 1. the ics clock generator is a slave/receiver, i 2 c component. it can read back the data stored in the latches for verification. read-back will support intel piix4 "block-read" protocol . 2. the data transfer rate supported by this clock generator is 100k bits/sec or less (standard mode) 3. the input is operating at 3.3v logic levels. 4. the data byte format is 8 bit bytes. 5. to simplify the clock generator i 2 c interface, the protocol is set to use only " block-writes " from the controller. the bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. the command code and byte count shown above must be sent, but the data is ignored for those two bytes. the data is loaded until a stop sequence is issued. 6. at power-on, all registers are set to a default condition, as shown. general i 2 c serial interface information the information in this section assumes familiarity with i 2 c programming. for more information, contact ics for an i 2 c programming application note. how to write: controller (host) sends a start bit. controller (host) sends the write address d2 (h) ics clock will acknowledge controller (host) sends a dummy command code ics clock will acknowledge controller (host) sends a dummy byte count ics clock will acknowledge controller (host) starts sending first byte (byte 0) through byte 5 ics clock will acknowledge each byte one at a time . controller (host) sends a stop bit how to read: controller (host) will send start bit. controller (host) sends the read address d3 (h) ics clock will acknowledge ics clock will send the byte count controller (host) acknowledges ics clock sends first byte (byte 0) through byte 5 controller (host) will need to acknowledge each byte controller (host) will send a stop bit notes: controller (host) ics (slave/receiver) start bit address d3 (h) a ck byte count ack byte 0 ack byte 1 ack byte 2 ack byte 3 ack byte 4 ack byte 5 ack stop bit how to read: controller (host) ics (slave/receiver) start bit address d2 (h) a ck dummy command code a ck dummy byte count a ck byte 0 a ck byte 1 ack byte 2 a ck byte 3 a ck byte 4 a ck byte 5 a ck stop bit how to write:
5 ics9250-19 third party brands and names are the property of their respective owners. t i bn o i t p i r c s e dd w p 7 t i b n o i t a l u d o m m u r t c e p s d a e r p s n w o d % 5 . 0 - o t 0 = 0 n o i t a l u d o m m u r t c e p s d a e r p s r e t n e c % 5 2 . 0 = 1 0 4 t i b 5 t i b 6 t i b 2 t i bk c o l c u p ci c p 1 e t o n , 2 t i b 4 : 6 t i b 1 1 1 0 0 1 1 0 0 . 0 0 1 3 3 1 ) 3 / u p c ( 3 4 . 3 3 ) 3 / u p c ( 3 3 . 4 4 1 0 1 0 0 0 1 0 2 1 1 3 0 1 ) 3 / u p c ( 3 3 . 7 3 ) 3 / u p c ( 3 . 4 3 1 1 0 0 0 1 0 0 6 . 6 6 3 . 3 8 ) 2 / u p c ( 4 . 3 3 ) 2 / u p c ( 5 6 . 1 4 1 0 0 0 0 0 0 0 5 7 4 2 1 ) 2 / u p c ( 5 . 7 3 ) 3 / u p c ( 3 3 . 1 4 1 1 1 1 0 1 1 1 3 3 1 4 2 1 ) 4 / u p c ( 5 2 . 3 3 ) 4 / u p c ( 0 0 . 1 3 1 0 1 1 0 0 1 1 0 5 1 0 4 1 ) 4 / u p c ( 0 5 . 7 3 ) 4 / u p c ( 0 0 . 5 3 1 1 0 1 0 1 0 1 5 0 1 0 1 1 ) 3 / u p c ( 0 0 . 5 3 ) 3 / u p c ( 7 6 . 6 3 1 0 0 1 0 0 0 1 5 1 1 0 2 1 ) 3 / u p c ( 3 3 . 8 3 ) 3 / u p c ( 0 0 . 0 4 3 t i b s t u p n i d e h c t a l , t c e l e s e r a w d r a h y b d e t c e l e s s i y c n e u q e r f - 0 ) e v o b a ( 4 : 6 t i b y b d e t c e l e s s i y c n e u q e r f - 1 0 1 t i b l a m r o n - 0 ) d a e r p s r e t n e c ( d e l b a n e m u r t c e p s d a e r p s - 1 1 0 t i b g n i n n u r - 0 s t u p t u o l l a e t a t s i r t - 1 0 byte0: functionality and frequency select register (default = 0) serial configuration command bitmap note: pwd = power-up default note 1. default at power-up will be for latched logic inputs to define frequency. bits 4, 5, 6 are default to 000, and if bit 3 is written to a 1 to use bits 6:4, then these should be defined to desired frequency at same write cycle.
6 ics9250-19 third party brands and names are the property of their respective owners. byte 1: cpu, active/inactive register (1= enable, 0 = disable) t i b# n i pd w pn o i t p i r c s e d 7 t i b-1 d e v r e s e r 6 t i b-1 d e v r e s e r 5 t i b-1 d e v r e s e r 4 t i b-1 d e v r e s e r 3 t i b6 41 ) t c a n i / t c a ( f _ m a r d s 2 t i b9 41 ) t c a n i / t c a ( 2 k l c u p c 1 t i b1 51 ) t c a n i / t c a ( 1 k l c u p c 0 t i b2 51 ) t c a n i / t c a ( f _ k l c u p c byte 2: pci, active/inactive register (1= enable, 0 = disable) t i b# n i pd w pn o i t p i r c s e d 7 t i b-1 d e v r e s e r 6 t i b81 ) t c a n i / t c a ( f k l c i c p 5 t i b6 11 ) t c a n i / t c a ( 5 k l c i c p 4 t i b4 11 ) t c a n i / t c a ( 4 k l c i c p 3 t i b3 11 ) t c a n i / t c a ( 3 k l c i c p 2 t i b2 11 ) t c a n i / t c a ( 2 k l c i c p 1 t i b1 11 ) t c a n i / t c a ( 1 k l c i c p 0 t i b91 ) t c a n i / t c a ( 0 k l c i c p notes: 1. inactive means outputs are held low and are disabled from switching. 2. latched frequency selects (fs#) will be inferted logic load of the input frequency select pin conditions. t i b# n i pd w pn o i t p i r c s e d 7 t i b-x # 0 s f d e h c t a l 6 t i b-1 d e v r e s e r 5 t i b-1 d e v r e s e r 4 t i b-x # 1 s f d e h c t a l 3 t i b-1 d e v r e s e r 2 t i b-1 d e v r e s e r 1 t i b-x # 3 s f d e h c t a l 0 t i b-1 d e v r e s e r byte 4: reserved , active/inactive register (1= enable, 0 = disable) t i b# n i pd w pn o i t p i r c s e d 7 t i b-1 d e v r e s e r 6 t i b-x # 2 s f d e h c t a l 5 t i b4 51 ) t c a n i / t c a ( f _ c i p a o i 4 t i b5 51 ) t c a n i / t c a ( 0 c i p a o i 3 t i b-1 d e v r e s e r 2 t i b-1 d e v r e s e r 1 t i b21 ) t c a n i / t c a ( 1 f e r 0 t i b31 ) t c a n i / t c a ( 0 f e r byte 5: peripheral , active/inactive register (1= enable, 0 = disable) byte 3: sdram, active/inactive register (1= enable, 0 = disable) t i b# n i pd w pn o i t p i r c s e d 7 t i b-1 d e v r e s e r 6 t i b-1 d e v r e s e r 5 t i b9 21 ) t c a n i / t c a ( z h m 8 4 4 t i b0 31 ) t c a n i / t c a ( z h m 4 2 3 t i b , 2 3 , 3 3 4 2 , 5 2 1) t c a n i / t c a ( ) 5 1 : 2 1 ( m a r d s 2 t i b , 1 2 , 2 2 8 1 , 9 1 1) t c a n i / t c a ( ) 1 1 : 8 ( m a r d s 1 t i b , 8 3 , 9 3 5 3 , 6 3 1) t c a n i / t c a ( ) 7 : 4 ( m a r d s 0 t i b , 3 4 , 4 4 0 4 , 1 4 1) t c a n i / t c a ( ) 3 : 0 ( m a r d s
7 ics9250-19 third party brands and names are the property of their respective owners. shared pin operation - input/output pins fig. 1 the i/o pins designated by (input/output) on the ics9250- 19 serve as dual signal functions to the device. during initial power-up, they act as input pins. the logic level (voltage) that is present on these pins at this time is read and stored into a 4-bit internal data latch. at the end of power-on reset, (see ac characteristics for timing values), the device changes the mode of operations for these pins to an output function. in this mode the pins produce the specified buffered clocks to external loads. to program (load) the internal configuration register for these pins, a resistor is connected to either the vdd (logic 1) power supply or the gnd (logic 0) voltage potential. a 10 kilohm(10k) resistor is used to provide both the solid cmos programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. figs. 1 and 2 show the recommended means of implementing this function. in fig. 1 either one of the resistors is loaded onto the board (selective stuffing) to configure the device?s internal logic. figs. 2a and b provide a single resistor loading option where either solder spot tabs or a physical jumper header may be used. these figures illustrate the optimal pcb physical layout options. these configuration resistors are of such a large ohmic value that they do not effect the low impedance clock signals. the layouts have been optimized to provide as little impedance transition to the clock signal as possible, as it passes through the programming resistor pad(s).
8 ics9250-19 third party brands and names are the property of their respective owners. fig. 2a fig. 2b
9 ics9250-19 third party brands and names are the property of their respective owners. cpu_stop# timing diagram cpustop# is an asychronous input to the clock synthesizer. it is used to turn off the cpuclks for low power operation. cpu_stop# is synchronized by the ics9250-19 . all other clocks will continue to run while the cpuclks are disabled. the cpuclks will always be stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse. cpuclk on latency is less than 4 cpuclks and cpuclk off latency is less than 4 cpuclks. notes: 1. all timing is referenced to the internal cpuclk. 2. cpu_stop# is an asynchronous input and metastable conditions may exist. this signal is synchronized to the cpuclks inside the ics9250-19. 3. ioapic output is stopped glitch free by cpustop# going low. 4. pci_stop# is shown in a high (true) state. 5. all other clocks continue to run undisturbed. notes: 1. all timing is referenced to the internal cpuclk (defined as inside the device.) 2. pci_stop# is an asynchronous input, and metastable conditions may exist. this signal is required to be synchronized inside the device. 3. all other clocks continue to run undisturbed. 4. cpu_stop# is shown in a high (true) state. pci_stop# timing diagram pci_stop# is an asynchronous input to the ics9250-19 . it is used to turn off the pciclk (0:5) clocks for low power operation. pci_stop# is synchronized by the ics9250-19 internally. pciclk (0:5) clocks are stopped in a low state and started with a full high pulse width guaranteed. pciclk (0:5) clock on latency cycles are only one rising pciclk clock off latency is one pciclk clock.
10 ics9250-19 third party brands and names are the property of their respective owners. absolute maximum ratings supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 v logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd ?0.5 v to v dd +0.5 v ambient operating temperature . . . . . . . . . . . . . 0c to +70c case temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 115c storage temperature . . . . . . . . . . . . . . . . . . . . . . . ?65c to +150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. electrical characteristics - input/supply/common output parameters t a = 0 - 70o c; supply voltage v dd = 3.3 v +/-5%, v ddl = 2.5 v +/-5% (unless otherwise stated) parameter s ymb o l co nditi o n s min typ max unit s input high voltage v ih 2v dd +0.3 v input low voltage v il v ss -0.3 0.8 v input high current i ih v in = v dd 0.1 5 n/a input frequency f i v dd = 3.3 v 12 14.318 16 mhz input capacitance 1 c in logic inputs 5 pf c inx x1 & x2 pins 27 36 45 pf transition time 1 t trans to 1st crossing of target freq. 4 ms settling time 1 t s from 1st crossing to 1% target freq. 1 3 ms clk s ta bili zat i on 1 t stab from v dd = 3.3 v to 1% target freq. 4ms 1 guaranteed by design, not 100% tested in production. ma electrical characteristics - input/supply/common output parameters t a = 0 - 70o c; supply voltage v dd = 3.3 v +/-5%, v ddl = 2.5 v +/-5% (unless otherwise stated) parameter symbol conditions min typ max units operating i dd2.5op100 select @ 100mhz; max discrete cap loads 13 25 supply current i dd2.5op133 select @ 133mhz; max discrete cap loads 18 25 1 guaranteed by design, not 100% tested in production. ma
11 ics9250-19 third party brands and names are the property of their respective owners. electrical characteristics - cpuclk t a = 0 - 7 0 o c ; v dd = 3 . 3 v + / - 5% , v ddl = 2 . 5 v + / - 5% ; c l = 20 pf ( un l ess ot h erw i se state d) parameter s ymb o l co nditi o n s min typ max unit s output high voltage v oh2b i oh = -12.0 ma 2 2.3 v output low voltage v ol2b i ol = 12 ma 0.2 0.4 v output high current i oh2b v oh = 1.7 v -41 -19 ma output low current i ol2b v ol = 0.7 v 19 37 ma rise time t r2b 1 v ol = 0.4 v, v oh = 2.0 v 0.4 1.6 ns fall time t f2b 1 v oh = 2.0 v, v ol = 0.4 v 0.4 1 1.6 ns duty cycle d t2b 1 v t = 1.25 v 45 51 55 % skew group1: 1,2 and 1,f t sk2b 1 v t = 1.25 v 120 175 ps skew group2: 2, f t sk2b 1 v t = 1.25 v 295 ps jitter, one sigma t j1 electrical characteristics - 48mhz, 24mhz,ref0 t a = 0 - 7 0 o c ; v dd = 3 . 3 v + / - 5% , v ddl = 2 . 5 v + / - 5% ; c l = 20 pf ( un l ess ot h erw i se state d) parameter symbol conditions min typ max units output high voltage v oh5 i oh = -14 ma 2.4 2.9 v output low voltage v ol5 i ol = 6.0 ma 0.25 0.4 v output high current i oh5 v oh = 2.0 v -42 -20 ma output low current i ol5 v ol = 0.8 v 10 18 ma rise time 1 t r5 v ol = 0.4 v, v oh = 2.4 v 1.1 2.5 ns fall time 1 t f5 v oh = 2.4 v, v ol = 0.4 v 1 2.5 ns duty cycle 1 d t5 v t = 1.5 v 45 50 55 % jitter 1 t j1s5 v t = 1.5 v, 24, 48mhz 100 250 ps ji tter 1 t jabs5 v t = 1.5 v, ref0 250 800 ps 1 guaranteed by design, not 100% tested in production.
12 ics9250-19 third party brands and names are the property of their respective owners. electrical characteristics - sdram t a = 0 - 70 o c; v dd = 3.3 v +/-5%, v ddl = 2.5 v +/-5%; c l =30 pf parameter symbol conditions min typ max units output high voltage v oh1 i oh = -28 ma 2.4 2.8 v output low voltage v ol1 i ol = 19 ma 0.34 0.4 v output high current i oh1 v oh = 2.0 v -72 -42 ma output low current i ol1 v ol = 0.8 v 33 50 ma ris e time 1 t r1 v ol = 0.4 v, v oh = 2.4 v 0.5 2 ns fall time 1 t f1 v oh = 2.4 v, v ol = 04 v 0.5 2.4 ns duty cycle 1 d t1 v t = 1.5 v 455055% skew(group1: f,0:4, 8:11) 1 t sk1 v t = 1.5 v 130 250 ps skew(group2: 5, 7, 12:15) 1 t sk1 v t = 1.5 v 180 250 ps skew(group3: 0, 13) 1 t sk1 v t = 1.5 v 490 ps skew(group4: 6, 13) 1 t sk1 v t = 1.5 v 910 ps skew(buferin-output) 1 t sk1 v t = 1.5 v 3.5 4.4 ns jitter, one sigma 1 t j1 1 v t = 1.5 v 50 150 ps jitter, absolute 1 t jabs1 v t = 1.5 v -250 130 250 ps 1 guaranteed by design, not 100% tested in production. electrical characteristics - pciclk t a = 0 - 70 o c; v dd = 3.3 v +/-5%, v ddl = 2.5 v +/-5%; c l = 60 pf for pci0 & pci1, cl = 30 pf for other pcis parameter symbol conditions min typ max units output high voltage v oh1 i oh = -18 ma 2.4 2.9 v output low voltage v ol1 i ol = 9.4 ma 0.2 0.4 v output high current i oh1 v oh = 2.0 v -58 -22 ma output low current i ol1 v ol = 0.8 v 25 52 ma ris e time 1 t r1 v ol = 0.8 v, v oh = 2.4 v 1.5 2.5 ns fall time 1 t f1 v oh = 2.4 v, v ol = 0.4 v 1.4 2.5 ns duty cycle 1 d t1 v t = 1.5 v 45 50 55 % skew 1 t sk1 v t = 1.5 v 270 500 ps jitter, one sigma 1 t j1 1 v t = 1.5 v 50 150 ps jitter, absolute 1 t jabs1 v t = 1.5 v 200 500 ps 1 guaranteed by design, not 100% tested in production.
13 ics9250-19 third party brands and names are the property of their respective owners. electrical characteristics - ioapic t a = 0 - 7 0 o c ; v dd = 3 . 3 v + / - 5% , v ddl = 2 . 5 v + / - 5% ; c l = 20 pf ( un l ess ot h erw i se state d) parameter symbol conditions min typ max units output high voltage v oh4b i oh = -12 ma 2 2.2 v output low voltage v ol4b i ol = 12 ma 0.3 0.4 v output high current i oh4b v oh = 1.7 v -32 -19 ma output low current i ol4b v ol = 0.7 v 19 26 ma rise time 1 t r4b v ol = 0.4 v, v oh = 2.0 v 0.4 1.5 1.8 ns fall time 1 t f4b v oh = 2.0 v, v ol = 0.4 v 0.4 1 1.6 ns duty cycle 1 d t4b v t = 1.25 v 45 51 55 % jitter, one sigma 1 t j 1
14 ics9250-19 third party brands and names are the property of their respective owners. general layout precautions: 1) use a ground plane on the top layer of the pcb in all areas not used by traces. 2) make all power traces and ground traces as wide as the via pad for lower inductance. notes: 1) all clock outputs should have a series terminating resistor, and a 20pf capacitor to ground between the resistor and clock pin. not shown in all places to improve readibility of diagram. 2) optional crystal load capacitors are recommended. they should be included in the layout but not inserted unless needed. component values: c1 : crystal load values determined by user c2 : 22f/20v/d case/tantalum avx tajd226m020r c3 : 100pf ceramic capacitor c4 : 20pf capacitor fb = fair-rite products 2512066017x1 all unmarked capacitors are 0.01f ceramic connections to vdd: = routed power = ground connection (component side copper) = ground plane connection = power route connection = solder pads = clock load ferrite bead vdd c2 22f/20v tantalum ferrite bead vdd c2 22f/20v tantalum c3 c3 1 clock load 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 2 c1 c1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 2.5v power route 3.3v power route 3.3v power route ground ground
15 ics9250-19 third party brands and names are the property of their respective owners. ordering information ics9250 y f-19 pattern number (2 or 3 digit number for parts with rom code patterns) package type f=ssop revision designator (will not correlate with datasheet revision) device type prefix ics, av = standard device example: ics xxxx y f - ppp ics reserves the right to make changes in the device data identified in this publication without further notice. ics advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate. index area index area 12 1 2 n d h x 45 h x 45 e1 e seating plane seating plane a1 a e -c- - c - b .10 (.004) c .10 (.004) c c l min max min max a 2 . 41 2 . 80 . 095 . 110 a1 0 . 20 0 . 40 . 008 . 016 b 0 . 20 0 . 34 . 008 . 0135 c 0 . 13 0 . 25 . 005 . 010 d e 10 . 03 10 . 68 . 395 . 420 e1 7 . 40 7 . 60 . 291 . 299 e h 0 . 38 0 . 64 . 015 . 025 l 0 . 50 1 . 02 . 020 . 040 n 300 mil ssop package

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